Most electronic devices in use today include many “chips” interconnected to provide a specific functionality. The chips generally comprise a semiconductor die embedded in a package, wherein each die may comprise an integrated circuit formed by standard semiconductor fabrication processes. The semiconductor die typically has a series of bond pads, which are used to make electrical contact to the integrated circuit formed therein. The die is placed on a carrier or substrate that has electrical leads formed therein to correspond to the bond pads of the die. The die and the carrier are enclosed to protect the die from the environment.
In memory structures, bond pads are large structures typically formed on the last metal line. To reduce costs, bond pads may also be formed as part of the last metal level. However, such structures impose additional limitations in metal line routing as the bond pads take up significant real estate on the metal level, adding significant constraints in the routing of metal lines. One way to overcome such limitation is to form bond pads over the last metal line, connected, for example, through a redistribution line. However, this introduces additional process steps. These additional process steps require expensive processing techniques such as lithography techniques, and e.g., subtractive metal patterning.
For almost 25 years, the semiconductor industry has rolled out a new generation of technology almost every two years, delivering improved performance at lower costs. One of the challenges faced in semiconductor manufacturing relates to reduction in process costs with each subsequent technology generation. Consequently, packaging processes also need to reduce fabrication costs with each technology generation. Hence, what are needed in the art are improved structures and methods for producing packages at lower costs.